Description of the MoM-PDA Project
Computer Structures Group, Kaiserslautern University
Aim of the proposed research project is the hardware realization of a new Xputer [HHW90] prototype called Map-oriented Machine with Parallel Data Access (MoM-PDA).
The Xputer is a novel, non-von Neumann paradigm, which uses data sequencing instead of instruction sequencing (but it is not a data flow machine, [HBH96]). The algorithm to be executed is configured once onto the hardware. As there are no further instructions at run time, only a data memory is required, which is organized 2-dimensionally. At run time an address stream is generated by a data sequencer. The accessed data is passed from the data memory through a smart interface to the reconfigurable ALU (rALU) and back. The smart interface is included into the rALU. It optimizes and reduces memory accesses by storing interim results and caching data needed several times. The figure shows all necessary components and their interconnect.
MoM-PDA machine overview:
This principles are derived from the fact that many computation-intensive applications iterate the same operations over a large amount of data. Xputers accelerate them by reducing the addressing overhead. All data needed for one computation step is held in the smart interface and can be accessed in parallel by the rALU. Furthermore with the dedicated hardwired Data Sequencer hardware no memory cycles are needed for address calculations.
The most important new feature of the MoM-PDA prototype will be parallel high speed access to the data. With the support of Xilinx we intend to implement the rALU of the new MoM-PDA with the new XC6k series. The programmable space of the XC6k device will be partitioned into two functional units. One unit will be the parallel memory interface for the MDRAMs [Sie96] and the smart interface. This unit is the same for every application and is configured once at power up. The remaining programmable space can be used in two different ways:
R. Hartenstein, J. Becker, M. Herz, U. Nageldinger: An Embedded Accelerator
for Real World Computing; accepted for publication in Proceedings of IFIP
International Conference on Very Large Scale Integration, VLSI`97, to be
held in Gramado, Brazil, August 26-29, 1997 .
[HB97] R. Hartenstein, J. Becker: A Two-level Co-Design Framework for data-driven Xputer-based Accelerators; published in Proc. of 30th Annual Hawaii Int'l Conf. on System Sciences (HICSS-30), Jan. 7-10, Wailea, Maui, Hawaii, 1997.
[HBH96] R. Hartenstein, J. Becker, M. Herz, U. Nageldinger: A General Approach in System Design Integrating Reconfigurable Accelerators; Proc. IEEE Int'l Conf. on Innovative Systems in Silicon; Austin, TX, Oct. 1996.
[HHW90] R. Hartenstein, A. Hirschbiel, M. Weber: A Novel Paradigm of Parallel Computation and its Use to Implement Simple High Performance Hardware; InfoJapan'90- Int'l. Conf. memorizing the 30th Anniv. of Computer Society Japan, Tokyo, Japan, 1990.
[Sie96] N.N.: Siemens Multibank DRAM, Ultra-high performance for graphic applications; Siemens Semicond. Group, Oct., 1996.
Any questions or suggestions? Please email to Michael
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